Description

This project is about building the fastest relay-cpu in the world.

Once you have a homebuilt CPU (and also before it is ready), everyone will ask: What can it do ? So it is important to have a good application to show what the CPU can do. That will also give some focus for the design.

I took a calculator as application. So the device should have calculator keys and a display. It will be a scientific calculator, using floating point calculations, and capable of logarithms and trigonometric functions.

The aim is a speed of a at most a few seconds for add and multiply, and at most 5 to 10 seconds for the scientific functions.

The design will have solid state memories, but might be prepared to work with a diode-ROM
and/or capacitor-RAM if the application does not need too much memory.

Details

How will the fast speed be accomplished ?

Relays are slow, and to get acceptable performance, many measures must be taken.

Architecture:

• Microcode will not be used
• Harvard architecture, so fetch and execute will be in parallel
• Have enough registers so we're not loading and storing all the time
• Have a good instruction set
• Some special instructions tailored to the algorithms that are used

Technology:

• Design in such a way that for executing an instruction a very low number of consecutive switching relays is needed. At this moment, there are only four consecutive switching relays for an instruction.
• Use small relays, these can be fast (datasheets show 2 msec switching time). Using small relays means they take less space on a pcb, so not much pcb area will be needed.

Now that all schematics and also all pcb's are designed, I can give a quite accurate listing of the number of main components:

• 327 relays
• 2296 diodes (1n4148)
• 51 diodes (1n4004)
• 259 LED's

The architecture is explained in the architecture document (see Files section). Highlights are:

• All instruction, register, word and memory sizes are 16 bit.
• Most instructions operate in a single cycle.
• There are eight 16-bit registers, one of them is the PC.
• Six registers can be paired to form three 32-bit registers (like the H and L registers in the 8080 / Z80 ). Many instructions have a 32-bit variant that operates on register pairs (using 2 cycles but single instruction word).
• It is a 2-operand design, 1 operand is a register and the other one can be register, memory, or immediate. If the immediate is only 8 bits (7bits + sign), it is included in the 16-bit opcode and the instruction executes in a single cycle.
• Memory addressing always has a small displacement within the instruction opcode, facilitating addressing of variables in a stack frame, or addressing of structure members. Instructions that use this need only a single cycle.
• The ALU has also decimal instructions (in addition to the normal binary instructions), to support the calculator functions.
• There is a special instruction to support (decimal) multiplication.
• The ALU has special instructions to convert the 4 nibbles in a register to bits that control a 7-segment display.

The architecture is independent from the technology, so it could also be used for a TTL or FPGA design. It can be upgraded to a full 32-bit design. Actually, since there are 32-bit register pairs, it would be easy to support a 32-bit address bus.

Use of the architecture is free for non-commercial use :), but I would like to get a mail when you are going to use it.

What has to be done:

• Have an architecture.
• Have a schematic.
• Have a simulation. The 4-bit boards have been low-level simulated in Logisim. I do not have a good logisim model for a relay, so the simulation might not catch all problems. Many instructions have also been simulated.
• Built an assembler and simulator. Simulating the application before the design is finished gives a chance to optimize the CPU for the application.
• PCB design
• PCB ordering
• Build an 8-bit version (this does not need all PCBs)
• Build a programmer for burning the flash memories
• Have a test strategy, and test.
• Find the causes of problems, and correct them. (now, may 2018)
• Build full 16-bit version

Block diagram

The design is shown in this block diagram (click on it for a larger version)

The block diagram also shows which functions the PCB's and the backplane contain.

Programming

A javascript assembler-simulator was built.
You can use it now at Risc Relay CPU Assembler

The software that is needed for the intended calculator can already be tested before the hardware is ready !

A Raspberry Pi runs the assembler-simulator in its webbrowser. It is connected to the Flash program memory with a small pcb (containing resistors for level conversion). It has a small Phyton program that burns the generated binary in the two Flash memories of the relay CPU.

Homebuilt CPUs WebRing

JavaScript by Qirien Dhaela

Join the ring?

To join the Homebuilt CPUs ring, drop Warren a line, mentioning your URL. He will then add it to the list. You will need to copy this code fragment into your page (or reference it.)
Note: The ring is chartered for projects that include a home-built CPU. It can emulate a commercial part, that′s OK. But actually using that commercial CPU doesn′t rate. Likewise, the project must have been at least partially built: pure paper designs don′t rate either. It can be built using any technology you like, from relays to FPGAs.