Source code

 
Simulator/Assembler updated 20181024.

One Square Inch CPU Assembler and Simulator

Microcode

Application simulation
0
PC
0000
 A
0000
 UPC
0000
RAM contents
0000 00 00 00 00 00 00 00 00
0008 00 00 00 00 00 00 00 00
0010 00 00 00 00 00 00 00 00
0018 00 00 00 00 00 00 00 00
0020 00 00 00 00 00 00 00 00
0028 00 00 00 00 00 00 00 00
0030 00 00 00 00 00 00 00 00
0038 00 00 00 00 00 00 00 00
0040 00 00 00 00 00 00 00 00
0048 00 00 00 00 00 00 00 00
0050 00 00 00 00 00 00 00 00
0058 00 00 00 00 00 00 00 00

ROELH - Thanks to Marco Schweighauser for the framework (2015) | MIT License | Blog